Scientific Research and Essays

  • Abbreviation: Sci. Res. Essays
  • Language: English
  • ISSN: 1992-2248
  • DOI: 10.5897/SRE
  • Start Year: 2006
  • Published Articles: 2768

Full Length Research Paper

Static synchronous series compensator and static var compensator interaction on voltage stability limit enhancement and active power loss minimization through differential evolution algorithm

  L. Jebaraj1*, C. Christober Asir Rajan2, K. Sriram1, J. Ramesh1 and R. Sivasankari1
    1Department of Electrical and Electronics Engineering, St. Anne’s College of Engineering and Technology, Panruti, Tamil Nadu, India. 2Department of Electrical and Electronics Engineering, Pondicherry Engineering College, Pillaichavadi, Puducherry, India.  
Email: [email protected]

  •  Accepted: 18 June 2013
  •  Published: 30 June 2013

Abstract

 

 

This paper proposes an application of differential evolution (DE) algorithm based extended voltage stability margin and minimization of real power loss incorporating static synchronous series compensator (SSSC) and static var compensator (SVC) devices. A new circuit element based model of SSSC and variable susceptance model of SVC are utilized to control the line power flows and bus voltage magnitudes for voltage stability limit improvement. The line stability index is used to assess the voltage stability of a power system. Voltage profile improvement values, real power loss minimization values and the location and size of SSSC and SVC devices were optimized by differential evolution algorithm. The results are obtained from the IEEE-30 Bus test case system and were analyzed with the voltage and real power loss under normal loading, critical loading and single line outage contingency conditions.

 

Key words: Differential evolution algorithm (DEA), voltage stability, static synchronous series   compensator (SSSC), static var compensator (SVC), line stability index, FACTS devices, load flow.